1. Field
The field of the embodiment relates to a technology for eliminating a high impedance state from a data strobe signal DQS outputted synchronously with a data signal DQ in a DDR SDRAM, and for generating a strobe signal for fetching the data signal DQ.
2. Description of the Related Art
In read-operation of the DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), data is outputted to a memory bus from the SDRAM synchronously with an edge of the data strobe signal DQS. At this time, the data strobe signal DQS having three values makes a transition from the high impedance state to a low level or high level. Meanwhile, a device for reading data fetches the data outputted to the memory bus synchronously with the edge of the data strobe signal DQS. Further, when the data is actually fetched by the device, an internal data strobe signal is used that the high impedance of the data strobe signal is masked from the data strobe signal. The level of the data strobe signal in the high impedance state becomes unstable and therefore a noise is easily mixed to the data strobe signal. That is why there is a risk that an erroneous fetch arises when the data strobe signal in such a state is used for a clock of data fetch.
An SDRAM interface circuit 100 shown in FIG. 14 is used as a technology for masking the high impedance state from the data strobe signal DQS.
The SDRAM interface circuit 100 includes: an RL count comparing part 101 to which a read instruction signal RD, a standby clock number RL and a clock signal CK are inputted and which outputs a BL count start signal BST; a BL count comparing part 102 to which the BL count start signal BST, a burst length BL and a fetch data strobe signal IDQS is inputted and which outputs a mask signal XMASK; and an AND gate 103 to which the mask signal XMASK and the data strobe signal DQS is inputted and which outputs the fetch data strobe signal IDQS.
The RL count comparing part 101 starts counting the clock signals CK when the read instruction signal RD is inputted thereto, and outputs the BL count start signal BST when the count value reaches the standby clock number RL. Here, a value of the standby clock number RL is set in advance.
When the BL count start signal BST is inputted to the BL count comparing part 102, the BL count comparing part 102 makes the mask signal XMASK active, starts counting the fetch data strobe signal IDQS and holds an active state of the mask signal XMASK until the count value reaches the burst length BL.
According to the above-described constitution, the SDRAM interface 100 starts counting the clock signals CK when the read instruction signal RD is inputted thereto, and makes the mask signal XMASK active by the number of clocks of the burst length BL when the count value reaches the standby clock number RL. The standby clock number RL is set in advance so that the data strobe signal DQS exceeds a period of the high impedance state. The high impedance of the data strobe signal DQS is thus masked, so an input of the data at the high impedance state to the fetch clock can be prevented.
Moreover, an art related to an SDRAM interface circuit is disclosed in Japanese unexamined patent publication No. 2003-85974.